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TDA8025
IC card interface
Rev. 01 -- 6 April 2009 Product data sheet
1. General description
The TDA8025 is a cost-effective analog interface for asynchronous smart cards operating at 3 V, 1.8 V or optionally, 1.2 V. Using few external components, the TDA8025 provides integrated supply, protection and control functions for a range of applications.
2. Features
I I I I I Integrated circuit smart card interface 3 V, 1.8 V or 1.2 V smart card supply Low power consumption in inactive mode Three protected, half duplex, bidirectional buffered input/output lines (C4, C7 and C8) VCC regulation: N 3 V, 1.8 V or optionally 1.2 V at 5 % using one 220 nF and one 470 nF low ESR multilayer ceramic capacitor. N Current pulse handling for pulses of 40 nAs at VCC = 3 V, 15 nAs at VCC = 1.8 V or VCC = 1.2 V up to 20 MHz Thermal and short-circuit protection for all card contacts Automatic activation and deactivation sequences triggered by short-circuit, card take-off, overheating, falling VDD(INTF) and VDD(INTREGD) Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV Clock signal using the internal oscillator or an external crystal ( 26 MHz) connected to pin XTAL1 Card clock generation up to 20 MHz with synchronous frequency changes of fxtal, 1 f 1 1 2 xtal, 4 fxtal or 8 fxtal using pins CLKDIV1 and CLKDIV2 Non-inverted control of pin RST using pin RSTIN NDS certified Supply supervisors during power on and off: N VDD(INTREGD) using a fixed threshold N VDD(INTF) using resistor bridge threshold adjustment Built-in debouncing on card presence contacts (typically 4.5 ms) Multiplexed status signal using pin OFFN
I I I I I I I I
I I
3. Applications
I I I I Pay TV Electronic payment Identification Bank card readers
NXP Semiconductors
TDA8025
IC card interface
4. Quick reference data
Table 1. Symbol Supplies VDDI(REG) regulator input supply voltage interface supply voltage pin CONFIG = ground pin CONFIG = VDDI(REG); regulator is bypassed pin CONFIG = ground pin CONFIG = VDDI(REG) and VDD(INTF) not connected to VDDI(REG) and VDD(INTREGD) pin CONFIG = VDDI(REG) with VDD(INTF) connected to VDDI(REG) and VDD(INTREGD) IDDI(REG) regulator input supply current inactive mode VDDI(REG) = 5 V; fxtal = stopped VDDI(REG) = 5 V; fxtal = 10 MHz; fCLK = 18 fXTAL active mode VCC = 3 V; ICC = 65 mA VCC = 1.8 V; ICC = 65 mA VCC = 1.2 V; ICC = 30 mA Card supply voltage VCC supply voltage including ripple inactive mode no load ICC = 1 mA active mode 3 V card: ICC < 65 mA DC single current pulse -100 mA; 2 s current pulses of 40 nAs at ICC < 200 mA; t < 400 ns 1.8 V card: ICC < 65 mA DC single current pulse -100 mA; 2 s current pulses of 15 nAs with ICC < 200 mA; t < 400 ns 1.2 V card: ICC < 30 mA DC single current pulse -100 mA; 2 s current pulses of 15 nAs with ICC < 200 mA; t < 400 ns Vripple(p-p) peak-to-peak ripple voltage pin VCC; 20 kHz to 200 MHz 1.1 1.1 1.10 1.2 1.2 1.2 1.3 1.3 1.3 350 V V V mV 1.71 1.66 1.66 1.83 1.83 1.83 1.89 1.94 1.94 V V V 2.85 2.76 2.76 3.05 3.05 3.05 3.15 3.20 3.20 V V V -0.1 -0.1 +0.1 +0.3 V V 85 85 50 mA mA mA 300 2.5 A mA
[1]
Quick reference data Parameter Conditions Min 3.6 3 1.6 1.6 3 Typ 5 3.3 3.0 3.0 3.3 Max 5.5 3.6 3.3 VDDI(REG) + 0.3 3.6 Unit V V V V V
VDD(INTF)
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TDA8025
IC card interface
Table 1. Symbol ICC
Quick reference data ...continued Parameter supply current Conditions 0 V to 3 V 0 V to 1.8 V 0 V to 1.2 V Min 0.02
[2]
Typ 0.14 80 -
Max 65 65 30 0.26 100 0.56 +85
Unit mA mA mA V/s s W C
SR General tdeact Ptot Tamb
[1]
slew rate deactivation time total power dissipation ambient temperature
up or down total sequence Tamb = -25 C to +85 C
35 -25
To enable the microcontroller to provide the required maximum voltage input level on XTAL1, VDD(INTF) must not exceed VDD(INTREGD) + 0.3 V. See Section 8.1 on page 7 for specific limitations on the maximum VDD(INTF) voltage and Table 8 on page 23 for the limits of XTAL1. See Figure 12 on page 18.
[2]
5. Ordering information
Table 2. Ordering information Package Name TDA8025HN HVQFN32 Description plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm Version SOT617-1 Type number
TDA8025_1
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Product data sheet
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TDA8025
IC card interface
6. Block diagram
VDDI(REG)
10 F
TEST2 TEST1 TEST4 3 TEST 32 TEST3 19 VDD(INTREGD) 24
GND 20
CONFIG 16
21 REGULATOR
2
100 nF 10 F
VDD(INTF) SUPPLY
R1 (1)
PORADJ 25
R2
INTERNAL REFERENCE VOLTAGE SENSE
INTERNAL OSCILLATOR CLKUP ALARMN EN1 PVCC
TDA8025
18 VCC VCC LOOP 14 CGND
470 nF
PRES PRESN
10 9
220 nF
RSTIN CMDVCCN OFFN CLKDIV1 CLKDIV2 ENCLKIN VCC_SEL1 VCC_SEL2
22 1
SEQUENCER EN4 EN3
RESET GENERATOR CLOCK GENERATOR
17 RST
23 6 5 26 7 8 INTERFACE
CLOCK CIRCUIT VDD(INTREGD) MULTIPLEXER
CLK
EN2
15 CLK
C5 THERMAL PROTECTION
Level shifter (VDD(INTF))
C1 C2 C3 C4
C6 I/O TRANSCEIVER I/O TRANSCEIVER 11 I/O C7 C8 13 AUX1
XTAL
OSCILLATOR (VDD(INTREGD))
220 nF
I/O TRANSCEIVER 31
12 AUX2
4
100 nF
27
28 XTAL1
29
30 AUX1UC
VDD(INTF)
XTAL2
I/OUC
AUX2UC
001aai957
(1) Optional external resistor bridge. If this bridge is not needed, connect pin PORADJ to VDD(INTF).
Fig 1.
Block diagram
TDA8025_1
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Product data sheet
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TDA8025
IC card interface
7. Pinning information
7.1 Pinning
26 ENCLKIN 31 AUX2UC 30 AUX1UC 25 PORADJ 24 TEST3 23 OFFN 22 RSTIN 21 VDDI(REG) 20 GND 19 VDD(INTREGD) 18 VCC 17 RST PRES 10 I/O 11 AUX2 12 AUX1 13 CGND 14 CLK 15 CONFIG 16 9
001aai958
32 TEST4
28 XTAL1
terminal 1 index area CMDVCCN TEST1 TEST2 VDD(INTF) CLKDIV2 CLKDIV1 VCC_SEL1 VCC_SEL2 1 2 3 4 5 6 7 8
TDA8025
PRESN
Transparent top view
Fig 2.
Pin configuration (HVQFN32)
7.2 Pin description
Table 3. Symbol CMDVCCN TEST1 TEST2 VDD(INTF) CLKDIV2 CLKDIV1 VCC_SEL1 Pin description Pin Type[1] Description 1 2 3 4 5 6 7 I I I P I I I microcontroller start activation sequence input; active LOW test pin; connect to GND test pin; connect to GND interface supply voltage sets the clock frequency; used together with pin CLKDIV1; see Table 4 on page 12 sets the clock frequency; used together pin CLKDIV2; see Table 4 on page 12 optional 1.2 V selection control signal: active HIGH: VCC = 1.2 V active LOW: disables 1.2 V selection VCC_SEL2 8 I 3 V or 1.8 V selection control signal: active LOW: VCC = 3 V active HIGH: VCC = 1.8 V when pin VCC_SEL1 is active LOW PRESN PRES I/O AUX2 AUX1
TDA8025_1
9 10 11 12 13
I I I/O I/O I/O
card presence contact input; active LOW[2] card presence contact input; active HIGH[2] card input/output data line (C7)[3] card auxiliary 2 input/output data line (C8)[3] card auxiliary 1 input/output data line (C4)[3]
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Product data sheet
Rev. 01 -- 6 April 2009
27 XTAL2
29 I/OUC
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TDA8025
IC card interface
Pin description ...continued Pin Type[1] Description 14 15 16 17 18 G O I O P card signal ground card clock (C3) 3.3 V or 5 V core regulator supply voltage selection; see Figure 3 on page 7 card reset (C2) card supply (C1); decouple to pin CGND using one 470 nF and one 220 nF capacitor with an Equivalent Series Resistance (ESR) < 100 m internally regulated supply voltage ground regulator input supply voltage microcontroller card reset input; active HIGH NMOS interrupt to microcontroller[4]; active LOW; see Section 8.10 on page 19 test pin; do not connect to the application power-on reset threshold adjustment input[4] enable external clock on pin XTAL1; active HIGH crystal connection pin; open when used with an external clock source crystal connection pin; supply reference VDD(INTREGD) external clock input; supply reference VDD(INTF) microcontroller input/output data line[4] microcontroller auxiliary 1 input/output data line[4] microcontroller auxiliary 2 input/output data line[4] test pin; connect to GND
Table 3. Symbol CGND CLK CONFIG RST VCC
VDD(INTREGD) 19 GND VDDI(REG) RSTIN OFFN TEST3 PORADJ ENCLKIN XTAL2 XTAL1 I/OUC AUX1UC AUX2UC TEST4
[1] [2] [3] [4]
P G P I O O I I O I I/O I/O I/O I
20 21 22 23 24 25 26 27 28 29 30 31 32
I = input, O = output, I/O = input/output, G = ground and P = power supply. If pin PRESN or pin PRES is true, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter this, the TDA8025 has a built-in debouncing timer (typically 4.5 ms). Using the internal pull-up resistor connected to pin VCC. Using the internal pull-up resistor connected to pin VDD(INTF).
TDA8025_1
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Product data sheet
Rev. 01 -- 6 April 2009
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TDA8025
IC card interface
8. Functional description
Remark: Throughout this document the ISO7816 terminology conventions have been adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
Two supply selections can be made using pin CONFIG (see Figure 3) depending on the active state of the pin:
* pin CONFIG is LOW: supply is pin VDDI(REG). The voltage range of the pin is between
3.6 V and 5.5 V. The regulator output range is between 3 V and 3.6 V.
* pin CONFIG is HIGH: supply pins VDDI(REG) and VDD(INTREGD) are connected together
to bypass the regulator. Pin VDDI(REG) voltage is between 3 V and 3.6 V. Remark: VDD(INTF) must not exceed VDD(INTREGD) + 0.3 V.
10 F 100 nF 10 F 100 nF
VDDI(REG)
10 F
VDDI(REG)
GND 20
CONFIG 16
VDD(INTREGD) 21 19
GND 20
CONFIG 16
VDD(INTREGD) 21 19
REGULATOR
REGULATOR
SUPPLY INTERNAL REFERENCE VOLTAGE SENSE VCC LOOP
SUPPLY INTERNAL REFERENCE
470 nF 220 nF
18 VCC 14 CGND
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18 VCC VCC LOOP
470 nF 220 nF
VOLTAGE SENSE
14 CGND
001aai960
3.6 V < VDDI(REG) < 5.5 V
3 V < VDD(INTREGD) < 3.6 V
Fig 3.
Power strategy
The following examples illustrate the voltage restrictions for VDD(INTF).
* CONFIG pin driven to GND: when VDD(INTREGD) is generated by the internal regulator,
VDD(INTF) must not exceed 3.3 V.
* CONFIG pin is driven by VDDI(REG) without VDD(INTF) tied to VDDI(REG) while
VDD(INTREGD) is tied to VDDI(REG): VDD(INTF) must not exceed VDDI(REG) + 0.3 V.
* CONFIG pin is driven by VDDI(REG) with VDD(INTF) tied to both VDDI(REG) and
VDD(INTREGD): there no are restrictions for VDD(INTF). The TDA8025 is held in the reset state until VDD(INTREGD) reaches Vth + Vhys and PORADJ Vth + Vhys plus the tw(POR) delay. If the VDD(INTREGD) and PORADJ signals fall below Vth, an automatic contact deactivation is triggered. All interface signals to the microcontroller are referenced to VDD(INTF). In addition, all card contacts remain inactive during power-up and power-down cycles.
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Product data sheet
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TDA8025
IC card interface
After powering up the device, pin OFFN remains LOW until pins CMDVCCN and PRES are both HIGH or pin CMDVCCN is HIGH and pin PRESN is LOW. During power off, pin OFFN is driven LOW when VDD(INTREGD) is below the falling threshold voltage (Vth). When pin CMDVCCN is HIGH, the internal oscillator frequency (fosc(int)) is switched to Low frequency (inactive) mode to reduce power consumption.
8.2 Voltage supervisors
8.2.1 Block diagram
VDD(INTF)
R1
PORADJ VDD(INTREGD) REFERENCE VOLTAGE
R2
VDD(INTREGD)
001aai961
Fig 4.
Voltage supervisor circuit
8.2.2 Description
The voltage supervisors provide both the Power-On Reset (POR) and supply drop-out detection functions. They control the internal regulated supply voltage (VDD(INTREGD)) and the microcontroller interface supply voltage (VDD(INTF)) to ensure problem-free operation of the TDA8025. By monitoring both VDD(INTREGD) and VDD(INTF), the voltage supervisors ensure these voltages are high enough to ensure correct operation of the TDA8025 and flawless communication between it and the microcontroller. This information is combined and sent to the digital controller in order to reset the TDA8025. An extension of the power-on reset pulse width of 8 ms (tw(POR)) is used to maintain the TDA8025 in inactive mode after the supply voltage power on or off sequences (see Figure 5).
Vth + Vhys Vth VDD(INTREGD) ALARMN (internal signal) Power on
tw(POR)
tw(POR) Supply dropout Power off
001aai962
Fig 5.
TDA8025_1
Voltage supervisors VDD(INTREGD) and VDD(INTF)
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Product data sheet
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TDA8025
IC card interface
8.2.3 VDD(INTREGD) voltage supervisor with pin PORADJ connected to VDD(INTF)
The TDA8025 remains in inactive mode irrespective of the levels on the command lines when
* VDD(INTREGD) is less than Vth + Vhys (on pin VDD(INTREGD)) * Pin PORADJ (monitoring VDD(INTF)) is less than Vth + Vhys
In both cases, this lasts for the duration of tw(POR) after VDD(INTREGD) (on pin VDD(INTREGD)) and VDD(INTF) (on pin VDD(INTF)) have reached a level higher than Vth + Vhys. Two threshold voltages (Vth) are set by the hardware as follows:
* VDD(INTREGD) threshold voltage: is set to the minimum supply voltage (2.7 V) specified
for the digital part of the TDA8025
* VDD(INTF) threshold voltage: is set to 1.24 V; see Table 8 on page 23 for detailed
information.
8.2.4 VDD(INTF) voltage supervisor with external divider on pin PORADJ
An external resistor bridge can be used to divide VDD(INTF) on pin PORADJ to adapt the detection threshold when monitoring the microcontroller interface supply voltage. Connecting the external resistor bridge as illustrated in Figure 4 on page 8 (R1 connected to VDD(INTF) and R2 connected to GND) to pin PORADJ overrides the internal threshold voltage Vth on pin VDD(INTF). The threshold voltage on pin VDD(INTF) is calculated as follows: 1 + R1 V th on pin V DD ( INTF ) = V bg --------------- R2 - where (1)
* Vbg is the bandgap voltage
When the resistor bridge is not used, pin PORADJ must be connected to pin VDD(INTF). 8.2.4.1 R1 and R2 resistor value calculation This section describes how to calculate the values for resistors R1 and R2, taking into account the IC detector threshold spread and the external resistance, while ensuring reliable activation. If for example, the controller is supplied by a regulator at 3.3 V 20 %. Activation can be triggered above VDD(INTF) = 3.3 V - 20 % (in this example 2.64 V). This activation threshold is defined as VDD(INTF)actmin; i.e. the minimum value of VDD(INTF) above which activation can always be triggered. In addition to this external input, activation is permitted provided all the following conditions are met (see Table 8 on page 23): card presence, IC temperature, VDD(INTF) and VDD(INTREGD) supplies, etc.
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Product data sheet
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TDA8025
IC card interface
The voltage on PORADJ (VPORADJ) can be calculated as: V PORADJ = x V DD ( INTF ) where:
* VDD(INTF) is the interface supply voltage * ratio
1 = --------------R1 1 + -----R2 An activation can be triggered if V th ( max ) V DD ( INTF ) x > V th ( max ) V DD ( INTF ) > ------------------ where (3) (2)
* Vth(max) is the maximum rising external threshold voltage
The resistance spread of R1 between a minimum value R1min and a maximum value R1max induces a spread of the ratio . This is also true for R2. Based on this: V th ( max V DD ( INTF )actmin = -------------------) min where 1 min = -----------------------R1 max 1 + -------------R2 min If R1 is the maximum spread of R1 and R2 is the maximum spread of R2 then: R1 R1 max = R1 nom + R1 = R1 nom 1 + -------------- R1 nom R2 R2 min = R2 nom - R2 = R2 nom 1 - -------------- R2 nom V th ( max ) 1 1 min = ----------------------------------------------------------- = ---------------------------------------------- = --------------------------------------R1 nom ( 1 + ) V DD ( INTF )actmin R1 R1 nom 1 + -------------- - 1 + ------------------------------------ R1 nom R2 nom ( 1 - ) 1 + -------------------------------------------------R2 R2 nom 1 - -------------- R2 nom where (6) (7) (5) (4)
(8)
* where is the accuracy ratio of R1 and R2 (R1 and R2 are considered to be of the
same type). Then
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Product data sheet
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TDA8025
IC card interface
R1 nom ( 1 - ) V DD ( INTF )actmin -------------- = ---------------- --------------------------------------- - 1 (1 + ) R2 nom V th ( max ) R sum R sum R2 nom = ------------------------------ = ------------------------------------------------------------------------------------------R1 nom (1 - ) 1 + -------------- 1 + ---------------- V DD ( INTF )actmin - 1 - -------------------------------------- (1 + ) R2 nom V th ( max )
(9)
(10)
If we target 1 % accuracy resistors ( = 0.01) and Rsum = 100 k; Vth(max) = 1.33 V (see Table 8 on page 23) and VDD(INTF)actmin = 2.64 V then
* R1nom = 50.88 k * R2nom = 49.12 k
Deactivation always occurs when V th ( min V PORADJ < V th ( min ) V DD ( INTF )deactmax = ------------------) max where (11)
* Vth(min) is the minimum falling external threshold voltage * VDD(INTF)deactmax is the maximum value of VDD(INTF) below which deactivation always
occurs
* max
V th ( min ) 1 max = ---------------------------------------------- = --------------------------------------------R1 nom ( 1 - ) V DD ( INTF )deactmax 1 + ------------------------------------R2 nom ( 1 + ) With the resulting values for R1nom, R2nom and ; Vth(min) = 1.17 V (see Table 8 on page 23) then VDD(INTF)deactmax is 2.28 V. (12)
8.3 Clock circuits
The clock signal (pin CLK) to the card is either generated by the clock signal input on pin XTAL1 or from a crystal (fxtal 26 MHz) connected between pins XTAL1 and XTAL2. The voltage level applied to pin ENCLKIN defines which clock signal is used. When pin ENCLKIN is HIGH, connect the external clock to pin XTAL1. Driving pin ENCLKIN LOW causes the external crystal to generate frequency fxtal. Using pins CLKDIV1 and CLKDIV2, the crystal frequency can be set to either fxtal, 12 fxtal, 14 fxtal or 18 fxtal. The frequency change is synchronous and as such during transition, no pulse is shorter than 45 % of the smallest period. In addition, only the first and last clock pulse around the change have the correct width. When dynamically changing the frequency, the modification is only effective after 10 periods of XTAL1.
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Product data sheet
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TDA8025
IC card interface
The duty cycle on pin CLK should be between 45 % and 55 %. To ensure this, the following must be applied:
* when the CLK frequency is fxtal:
If an external clock is connected to pin XTAL1, the duty cycle should be between 48 % and 52 % with an input signal period transition time of less than 5 %. If a crystal is used to generate fxtal, the duty cycle on pin CLK should be between 45 % and 55 % depending on the layout, crystal characteristics and frequency.
* when CLK frequency is either fxtal, 12 fxtal, 14 fxtal or 18 fxtal:
The duty cycle is guaranteed between 45 % and 55 % of the period frequency divisions. When a crystal is used, it runs when pin ENCLKIN is driven LOW.
CLKDIV1 6 CLKDIV2 5 CLOCK CIRCUIT 15 CLK
ENCLKIN 26 MULTIPLEXER
XTAL
OSCILLATOR
27 XTAL2
28 XTAL1
26 MHz(1)
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(1) External crystal (optional).
Fig 6.
Clock circuits
The clock signal is applied to the card based on the activation sequence as shown on the timing diagrams; see Figure 8 on page 15 to Figure 13 on page 19. When the signal applied to XTAL1 is controlled by the microcontroller, the clock signal is sent to the card only after the activation sequence finishes.
Table 4. Clock configuration Clock circuitry definition (pins CLKDIV1 and CLKDIV2 can be changed simultaneously; a >10 XTAL1 period delay is needed. The minimum duration of any CLK state is 10 XTAL1 periods). CLKDIV1 0 0 1 1 CLKDIV2 0 1 1 0 CLK
1 1 1 8 fxtal 4 fxtal 2 fxtal
fxtal
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Product data sheet
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TDA8025
IC card interface
8.4 Input and output circuits
When pins I/O and I/OUC are driven HIGH using an 11 k resistor between pins I/O and VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC VDD(INTF). The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables falling edge detection on the other line, making it the slave. After a time delay td(edge), the NMOS transistor on the slave-side is turned on. It then sends logic 0 to the master-side. When the master returns logic 1, the PMOS transistor on the slave side is turned on during the time delay (tpu). After this sequence, both the master and slave return to their idle states. The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8025 capable of delivering more than 1 mA, up to an output voltage of 0.9 VCC, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the internal pull-up resistor value and load current. The current sent to and received from the card's I/O lines is internally limited to 15 mA at a maximum frequency of 1 MHz.
8 IOH I/O (A) 6 IOH I/O V I/O
001aai964
4 V I/O (V) 3
4
2
2
1
0 0 20 40 60 80 t (ns)
0 100
Fig 7.
Output voltage and current on pins I/O, AUX1 and AUX2 as a function of time during LOW-to-HIGH transitions
8.5 Inactive mode
After a power-on reset, the circuit enters the inactive mode, ensuring only the minimum number of circuits are active while the TDA8025 waits for the microcontroller to start a session. The inactive mode conditions are as follows:
* all card contacts are inactive. The impedance between the contacts and GND is
approximately 200 .
* pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 k pull-up
resistor connected to VDD(INTF)
* the voltage generators and crystal oscillator are stopped * the voltage supervisor is active * the internal oscillator runs in low frequency mode
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Product data sheet
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TDA8025
IC card interface
8.6 Activation sequence
After the power-on and internal pulse width delay, the microcontroller checks the presence of the card using signal OFFN.
* The card is present when pins OFFN and CMDVCCN are HIGH * The card is not present when pin OFFN is LOW and pin CMDVCCN is HIGH
If the card is in the reader (either pin PRESN or pin PRES is true), the microcontroller can start a card session by pulling pin CMDVCCN LOW. When using an external crystal, the following sequence is applied (see Figure 8): 1. pin CMDVCCN is pulled LOW (t0) 2. the crystal oscillator is triggered 3. the internal oscillator changes to its high frequency (t1) 4. VCC rises either from 0 V to 3 V or 1.8 V on a controlled slope (t2) 5. pins I/O, AUX1 and AUX2 which were pulled LOW are driven HIGH (t3) 6. the clock (pin CLK) is applied to the C3 contact (t4) 7. pin RST is enabled (t5) Calculation of the time delays is as follows:
* * * * *
t1 = t0 + 2.13 ms t2 = t1 t3 = t1 + 5T/2 t4 = driven by host controller; > t3 and < t5 t5 = t1 + 11T/2
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. 25 s. t3 is called td(start) and t5 is called td(end). The clock is applied to the card in one of the following ways:
* using pin RSTIN: The clock (pin CLK) start-up can be selected at either t3 or t5 using
pin RSTIN. When pin RSTIN is HIGH and pin CMDVCCN is LOW, setting pin RSTIN to LOW between delays t3 and t5 sends signal CLK. Pin RSTIN should be held LOW until after delay t5. After passing t5, pin RST is a copy of pin RSTIN and has no further effect on pin CLK. It enables the microcontroller to precisely choose the CLK start by counting clock cycles from the falling edge of the RSTIN signal.
* not using pin RSTIN: If this feature is not needed, set both pins CMDVCCN and
RSTIN to LOW. The clock (pin CLK) will start at delay t3 (a minimum 200 ns after the input/output transition). After delay t5, pin RSTIN can be set HIGH to receive the card Answer To Request (ATR). Remark: Do not perform activation with pin RSTIN permanently pulled HIGH.
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IC card interface
CMDVCCN XTAL VCC I/O ATR
CLK
RSTIN
RST
I/OUC
OSCINT
low frequency t0 t1 = t2 td(start) t4 td(end) = tact
high frequency
001aai965
Fig 8.
Activation sequence: CLK controlled by pin RSTIN with the crystal oscillator
CMDVCCN XTAL VCC I/O ATR
CLK > 200 ns RSTIN
RST
I/OUC
OSCINT
low frequency t0 t1 = t2 t4 td(start) td(end) = tact
high frequency
001aai966
Fig 9.
Activation sequence: CLK not controlled by pin RSTIN with the crystal oscillator
The following sequence occurs when using an external clock connected to pin XTAL1 (see Figure 10): 1. external clock (XTAL1) started by the microcontroller (t0) 2. CMDVCCN is pulled LOW and the internal oscillator changes to its high frequency (t1) 3. VCC rises either from 0 V to 3 V or 0 V to 1.8 V on a controlled slope (t2)
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TDA8025
IC card interface
4. pins I/O, AUX1 and AUX2 are enabled (t3) 5. CLK is applied to the C3 contact (t4) 6. pin RST is enabled (t5) Calculation of the time delays is as follows:
* * * * *
t1 = t0 + 2.13 ms t2 = t1 = 3T/2 + 3(1fosc(int)low) t3 = t1 + 5T/2 t4 = driven by the host controller; > t3 and < t5 t5 = t1 + 11T/2
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. 25 s). t3 is called td(start) and t5 is called td(end). fosc(int)low is the low (or inactive mode) frequency of the defined fosc(int) parameter. The CLK is applied to the card under control of pin RSTIN in exactly the same way as with the crystal oscillator. Remark: Do not perform activation with pin RSTIN permanently pulled HIGH.
CMDVCCN XTAL1 VCC I/O ATR
CLK
RSTIN
RST
I/OUC
OSCINT
low frequency t0 t1 = t2 td(start) t4 td(end) = tact
high frequency
001aai967
Fig 10. Activation sequence: CLK controlled by pin RSTIN with an external clock connected to pin XTAL1
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IC card interface
CMDVCCN XTAL1 VCC I/O ATR
CLK > 200 ns RSTIN
RST
I/OUC
OSCINT
low frequency t0 t1 = t2 t4 td(start) td(end) = tact
high frequency
001aai968
Fig 11. Activation sequence: CLK not controlled by pin RSTIN and with an external clock connected to pin XTAL1
8.7 Active mode
When the activation sequence has finished, the TDA8025 is in active mode. This mode enables data exchange between the card and the microcontroller using the input and output lines. Depending on the layout and application test conditions, line C2 could become polluted with high frequency noise from line C3. For example, due to an additional 1 pF capacitance between lines C2/C3 and/or lines C2/C7. It is recommended that a 100 pF capacitor is added between line C2 and pin CGND, if this occurs. When building the application, the following recommendations should be adhered to:
* Keep track C3 as far away as possible from other tracks. * Keep the connection between pin CGND and line C5 straight. The two capacitors on
line C1 should be connected to this ground track.
* Do not use ground loops between CGND and GND.
Following these layout recommendations will ensure that noise remains within the specifications and jitter on line C3 is less than 100 ps.
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8.8 Deactivation sequence
When a session is completed, the microcontroller sets pin CMDVCCN to HIGH. The circuit then executes an automatic deactivation sequence by counting the sequencer back to the inactive state (see Figure 12 and Figure 13): 1. pin RST is pulled LOW (t11) 2. the clock is stopped, pin CLK is LOW (t12) 3. pins I/O, AUX1 and AUX2 are pulled LOW (t13) 4. VCC falls to zero (t14). The deactivation sequence is completed when VCC reaches its inactive state 5. all card contacts become low-impedance to GND. However, pins I/OUC, AUX1UC and AUX2UC remain pulled up to VDD(INTREGD) using the 11 k resistor 6. The internal oscillator returns to its low frequency mode Calculation of the time delays is as follows:
* * * *
t11 = t10 + 3T/64 t12 = t11 + T/2 t13 = t11 + T t14 = t11 + 3T/2
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. 25 s).
CMDVCCN RST
CLK I/O VCC XTAL
OSCINT t10 t11
high frequency t12 t13 tdeact t14
low frequency
001aai969
Fig 12. Deactivation sequence with a crystal oscillator
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CMDVCCN RST
CLK I/O VCC XTAL1
OSCINT t10 t11
high frequency t12 t13 tdeact t14
low frequency
001aai970
Fig 13. Deactivation sequence with an external clock connected to pin XTAL1
8.9 VCC regulator
Table 5. 0 0 1 1 Selection of VCC using pins VCC_SEL1 and VCC_SEL2 VCC_SEL2 0 1 0 1 VCC 3V 1.8 V 1.2 V 1.2 V VCC_SEL1
The VCC buffer is able to continuously deliver up to:
* 65 mA at 3 V * 65 mA at 1.8 V * 30 mA at 1.2 V
The VCC buffer has an internal overload protection with a threshold value of 135 mA. This detection is filtered, enabling spurious current pulses up to 200 mA with a duration of up to 200 ns to be drawn by the card without causing deactivation. However, the average current value must be below maximum. To enhance VCC stability, one 470 nF capacitor should be tied to pin CGND near pin 18 and one 220 nF capacitor should be tied to pin CGND near the C1 contact. Both capacitors should have an ESR < 100 m.
8.10 Fault detection
The following conditions are monitored by the fault detection circuit:
* Short-circuit or high current on pin VCC * Card removal during transaction * VDD(INTREGD) falling
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IC card interface
* VDD(INTF) falling * Overheating
Fault detection monitors two different situations (see Figure 15 on page 21): 1. Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in the reader and HIGH if the card is in the reader. Any supply voltage drop on VDD(INTREGD) or VDD(INTF) is detected by the supply supervisor. This generates an internal power-on reset pulse but does not act upon the pin OFFN signal. The card is not powered-up and as such short-circuits and overheating are not detected. 2. Within card sessions, pin CMDVCCN is LOW: when pin OFFN falls LOW, the fault detection circuit triggers the automatic emergency deactivation sequence (see Figure 14). When the system controller resets pin CMDVCCN to HIGH, after the deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN returns to HIGH. This check identifies the fault as either a hardware problem or a card removal incident. On card insertion or removal, bouncing can occur in the PRES and/or PRESN signals. This depends on the type of card presence switch in the connector (normally open or normally closed) and the mechanical characteristics of the switch. To correct for this, a debouncing feature is integrated in to the TDA8025. This feature operates at a typical duration of 640 x (1fosc(int)low). See Figure 15 for an overview of the debouncing feature. Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int) parameter. On card insertion, pin OFFN goes HIGH after the debouncing time has elapsed. When the card is extracted, the automatic card deactivation sequence is performed on the first true or false transition on pin PRESN or pin PRES. After this pin OFFN goes LOW.
OFFN PRESN
RST CLK I/O VCC XTAL
OSCINT t10
high frequency t12 t13 tdeact t14
low frequency
001aai971
Fig 14. Emergency deactivation sequence after card removal
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IC card interface
PRES
OFFN
CMDVCCN tdeb VCC
(1)
tdeb
(2)
001aai972
(1) Deactivation caused by card removal. (2) Deactivation caused by short circuit.
Fig 15. Operation of debounce feature pin OFFN in combination with pins CMDVCCN, PRES and VCC
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9. Limiting values
Remark: All card contacts are protected against any short-circuit to any other card contact. Stress beyond the levels indicated in Table 6 can cause permanent damage to the device. This is a short-term stress rating only and under no circumstances implies functional operation under long-term stress conditions.
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDI(REG) VI Parameter regulator input supply voltage input voltage pins CMDVCCN, TEST1, TEST2, CLKDIV2, CLKDIV1, VCC_SEL1, VCC_SEL2, CONFIG, RSTIN, OFFN, TEST3, PORADJ, ENCLKIN, XTAL2, XTAL1, I/OUC, AUX1UC and AUX2UC card contact pins PRES, PRESN, I/O, RST, AUX1, AUX2 and CLK Tstg Ptot Tj Tamb VESD storage temperature total power dissipation junction temperature ambient temperature electrostatic discharge voltage pins I/O, RST, VCC, AUX1, CLK, AUX2, PRES and PRESN; within typical application Human Body Model (HBM); all pins; EIA/JESD22-A114-B, June 2000 Machine Model (MM); all pins; EIA/JESD22-A115-A, October 1997 Charged Device Model (CDM); all pins, except corner pins only corner pins (1, 8, 9, 16, 17, 24, 25 and 32) -500 -750 +500 +750 V V Tamb = -25 C to +85 C Conditions Min -0.3 -0.3 -0.3 Max +5.5 +5.5 +5.5 Unit V V V
VDD(INTREGD) internal regulated supply voltage
-0.3 -55 -25 -6
+6.5 +150 0.56 150 +85 +6
V C W C C kV
-2 -200
+2 +200
kV V
10. Thermal characteristics
Table 7. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions with exposed pad soldered without exposed pad soldered Typ 42 62 Unit K/W K/W
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IC card interface
11. Characteristics
Table 8. Characteristics of IC supply voltage Tamb = 25 C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol Supply VDDI(REG) regulator input supply voltage pin CONFIG = ground pin CONFIG = VDDI(REG); regulator is bypassed
[1]
Parameter
Conditions
Min 3.6 3 3
Typ 5 3.3 3.3
Max 5.5 3.6 3.6
Unit V V V
VDD(INTREGD)
internal pin CONFIG = ground regulated supply voltage interface supply voltage pin CONFIG = ground pin CONFIG = VDDI(REG) and VDD(INTF) not connected to VDDI(REG) and VDD(INTREGD) pin CONFIG = VDDI(REG) with VDD(INTF) connected to VDDI(REG) and VDD(INTREGD)
VDD(INTF)
[2]
1.6 1.6
3.0 3.0
3.3 VDDI(REG) + 0.3
V V
3
3.3
3.6
V
IDDI(REG)
regulator input supply current
inactive mode VDDI(REG) = 5 V fxtal = stopped VDDI(REG) = 5 V fxtal = 10 MHz; fCLK = 18 fxtal active mode VCC = 3 V; ICC = 65 mA VCC = 1.8 V; ICC = 65 mA VCC = 1.2 V; ICC = 30 mA 2.60 2.65 1.17 1.19 50 5 2.70 2.80 1.24 1.26 100 8 85 85 50 100 2.80 2.95 1.31 1.33 150 18 0.25 mA mA mA A V V V V mV ms mV/C 300 2.5 A mA
IDD(INTF) Vth
interface supply current threshold voltage pin VDD(INTREGD); falling pin VDD(INTREGD); rising pin PORADJ; falling pin PORADJ; rising
Vhys tw(POR) Vth/T
hysteresis voltage power-on reset pulse width threshold voltage variation with temperature
pin VDD(INTREGD)
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IC card interface
Table 8. Characteristics of IC supply voltage ...continued Tamb = 25 C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol IL Card supply Cdec VCC Parameter leakage current voltage[3] decoupling capacitance supply voltage connected to VCC including ripple inactive mode no load ICC = 1 mA active mode 3 V card: ICC < 65 mA DC single current pulse -100 mA; 2 s current pulses of 40 nAs at ICC < 200 mA; t < 400 ns 1.8 V card: ICC < 65 mA DC single current pulse -100 mA; 2 s current pulses of 15 nAs with ICC < 200 mA; t < 400 ns 1.2 V card: ICC < 30 mA DC single current pulse -100 mA; 2 s current pulses of 15 nAs with ICC < 200 mA; t < 400 ns Vripple(p-p) ICC peak-to-peak ripple voltage supply current pin VCC; 20 kHz to 200 MHz 0 V to 3 V 0 V to 1.8 V 0 V to 1.2 V SR Cext slew rate external capacitance up or down pins XTAL1/XTAL2; depending on the crystal or resonator specification Crystal oscillator: pins XTAL1 and XTAL2 15 pF 1.1 1.1 1.10 1.2 1.2 1.2 1.3 1.3 1.3 V V V 1.71 1.66 1.66 1.83 1.83 1.83 1.89 1.94 1.94 V V V 2.85 2.76 2.76 3.05 3.05 3.05 3.15 3.20 3.20 V V V -0.1 -0.1 +0.1 +0.3 V V 550 830 nF Conditions pin PORADJ < 0.5 V pin PORADJ > 1 V Min -0.1 -1 Typ +4 Max +10 +1 Unit A A
0.02
0.14
350 65 65 30 0.26
mV mA mA mA V/s
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IC card interface
Table 8. Characteristics of IC supply voltage ...continued Tamb = 25 C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol fxtal fext VIL VIH Parameter Conditions Min 2 0 -0.3 Typ Max 26 26 +0.3VDD(INTF) Unit MHz MHz V crystal frequency card clock reference; crystal oscillator external frequency LOW-level input voltage HIGH-level input voltage external clock on pin XTAL1 pin XTAL1 pin XTAL1 VDD(INTF) VDD(INTREGD) VDD(INTF) > VDD(INTREGD) td tw(pu) fio Ci delay time pull-up pulse width input/output frequency input capacitance output voltage on data lines on data lines falling edge on pins I/O and I/OUC or vise versa 0.7VDD(INTF) 0.7VDD(INTF) VDD(INTF) + 0.3 VDD(INTREGD) + 0.3 200 100 1 10 V V
Data lines: pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC ns ns MHz pF
Data lines to the card: pins I/O, AUX1 and AUX2[4] Vo inactive mode no load Io = 1 mA Io output current from data lines when in inactive mode with pins grounded 0 0.1 0.3 -1 V V mA
VOL VOH
LOW-level output IOL = 1 mA voltage IOL 15 mA HIGH-level output voltage no DC load IOH < -40 A; 3 V IOH < -20 A; 1.8 V or 1.2 V card current limit IOH = -15 mA
0 VCC - 0.4 0.9VCC 0.75VCC 0.75VCC 0 -0.3 -0.3 -0.3 0.6VCC
350 -
0.3 VCC VCC + 0.1 VCC + 0.1 VCC + 0.1 0.4 +0.8 +0.6 +0.4 VCC + 0.3 600
V V V V V V V V V V mV A
(c) NXP B.V. 2009. All rights reserved.
VIL
LOW-level input voltage
VCC = +3 V VCC = +1.8 V VCC = +1.2 V
VIH Vhys IIL
TDA8025_1
HIGH-level input voltage hysteresis voltage LOW-level input current pin I/O pin I/O; VIL = 0 V
-
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IC card interface
Table 8. Characteristics of IC supply voltage ...continued Tamb = 25 C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol IIH tr(i) tr(o) tf(i) tf(o) Rpu IOH Parameter HIGH-level input current input rise time output rise time input fall time output fall time pull-up resistance HIGH-level output current Conditions pin I/O; VIH = VCC VIL maximum to VIH minimum CL 80 pF; 10 % to 90 %; 0 V to VCC VIL maximum to VIH minimum CL 80 pF; 10 % to 90 %; 0 V to VCC between I/O and VCC pin I/O when active pull-up; VOH = 0.9VCC; C = 80 pF Min 8 -8 Typ 11 -6 Max 10 1.2 0.1 1.2 0.1 13 -4 Unit A s s s s k mA
Data lines to the system: pins I/OUC, AUX1UC and AUX2UC[5] VOL VOH LOW-level output IOL = 1 mA voltage HIGH-level output voltage no DC load IOH 40 A; VDD(INTF) > 2 V IOH 20 A; VDD(INTF) < 2 V VIL VIH Vhys IIH IIL Rpu tr(i) tr(o) tf(i) tf(o) LOW-level input voltage HIGH-level input voltage hysteresis voltage HIGH-level input current LOW-level input current pull-up resistance input rise time output rise time input fall time output fall time pin I/OUC pin I/OUC; VIH = VDD(INTF) pin I/OUC; VIL = 0 V between I/OUC and VDD(INTF) VIL maximum to VIH minimum CL 80 pF; 10 % to 90 %; 0 V to VCC VIL maximum to VIH minimum CL 80 pF; 10 % to 90 %; 0 V to VCC 0 0.9VDD(INTF) 0.75VDD(INTF) 0.75VDD(INTF) -0.3 0.7VDD(INTF) 8 0.19VDD(INTF) 11 0.3 VDD(INTF) + 0.1 VDD(INTF) + 0.1 VDD(INTF) + 0.1 +0.3VDD(INTF) VDD(INTF) + 0.3 10 600 13 1.2 0.1 1.2 0.1 V V V V V V V A A k s s s s
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IC card interface
Table 8. Characteristics of IC supply voltage ...continued Tamb = 25 C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol IOH Parameter HIGH-level output current Conditions pin I/OUC when active pull-up; VOH = 0.9VDD; C = 30 pF Min -1 Typ Max Unit mA
Internal oscillator fosc(int) internal oscillator inactive mode frequency active mode output voltage inactive mode no load Io = 1 mA Io td VOL VOH tr tf output current delay time when inactive and pin RST grounded between pins RSTIN and RST; RST enabled 0 0 0 VCC - 0.4 0.9VCC 0
[6]
55 1.9
140 2.7
200 3.2
kHz MHz
Reset output to the card: pin RST Vo 0.1 0.3 -1 2 0.2 VCC VCC 0.4 0.1 0.1 V V mA s V V V V s s
LOW-level output IOL = 200 A voltage current limit IOL = 20 mA HIGH-level output voltage rise time fall time IOH = -200 A current limit IOH = -20 mA CL = 100 pF; VCC = 3 V, 1.8 V or 1.2 V CL = 100 pF; VCC = 3 V, 1.8 V or 1.2 V inactive mode no load Io = 1 mA
-
[6]
Clock output to the card: pin CLK Vo output voltage 0 0 0 VCC - 0.4 0.9VCC 0
[6] [6] [6]
-
0.1 0.3 -1 0.3 VCC VCC 0.4 16 16 55 -
V V mA V V V V ns ns % V/ns V/ns
Io VOL VOH tr tf SR
output current
pin CLK when inactive and grounded
LOW-level output IOL = 200 A voltage current limit IOL = 70 mA HIGH-level output voltage rise time fall time duty cycle slew rate IOH = -200 A current limit IOH = -70 mA CL = 30 pF CL = 30 pF except for fxtal; CL = 30 pF rise and fall; CL = 30 pF; VCC = 3 V or 1.8 V CL = 30 pF; VCC = 1.2 V
45 0.2 0.1
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IC card interface
Table 8. Characteristics of IC supply voltage ...continued Tamb = 25 C; all parameters remain within limits but are only statistically tested for the temperature range; fxtal = 10 MHz; all currents flowing into the IC are positive; unless otherwise specified. Parameters specified as a function of VDD(INTF), VDDI(REG), VDD(INTREGD) or VCC refer to the actual value at the time of measurement. Symbol VIL VIH Vhys IIL IIH Parameter LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level input current HIGH-level input current frequency on pin CMDVCCN LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level input current HIGH-level input current pins PRES and PRESN VIL = 0 V VIH = VDD(INTREGD) pin CONFIG VIL = 0 V VIH = VDD(INTREGD) control inputs VIL = 0 V VIH = VDD(INTF) Conditions Min -0.3 0.7VDD(INTF) Typ 0.14VDD(INTF) Max ENCLKIN[7] +0.3VDD(INTF) VDD(INTF) + 0.3 1 1 V V V A A Unit Control inputs: pins CLKDIV1, CLKDIV2, CMDVCCN, RSTIN, VCC_SEL2, VCC_SEL1 and
Control inputs CMDVCCN and CONFIG[7] fCMDVCCN VIL VIH Vhys IIL IIH -0.3 0.7 VDD(INTREGD) 0.14VDD(INTF) 150 +0.3VDD(INTF) VDD(INTREGD) + 0.3 1 1 kHz V V V A A
Card detection inputs: pins PRES and PRESN[7][8][9] VIL VIH Vhys IIL IIH -0.3 0.7 VDD(INTREGD) 0.17 VDD(INTREGD) +0.3VDD(INTREGD) V VDD(INTREGD) + 0.3 5 5 V V A A
OFFN output[10]: pin OFFN VOL VOH Rpu LOW-level output IOL = 2 mA voltage HIGH-level output voltage pull-up resistance IOH = -15 A to VDD 0 0.75VDD(INTF) 16 20 0.3 24 V V k
[1]
Two decoupling capacitors connected in parallel to VDD(INTREGD) rated at 100 nF and 1 F.
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IC card interface
[2]
To enable the microcontroller to provide the required maximum voltage input level on XTAL1, VDD(INTF) must not exceed VDD(INTREGD) + 0.3 V. See Section 8.1 on page 7 for specific limitations on the maximum VDD(INTF) voltage and Table 8 on page 23 for the limits of XTAL1. To meet these specifications, VCC should be decoupled to pin CGND using two low ESR, ceramic multilayer capacitors one of 470 nF and one of 220 nF with an ESR of < 100 m. Using the internal pull-up resistor to VCC. Using the internal pull-up resistor to VDD(INTF). The transition time and the duty factor definitions are shown in Figure 16 on page 30; = t1/(t1 + t2). Pins PRESN and CMDVCCN are active LOW. Pins RSTIN and PRES are active HIGH; see Table 4 on page 12 for pins CLKDIV1 and CLKDIV2; see Table 5 on page 19 for pins VCC_SEL1 and VCC_SEL2. If PRESN or PRES is true, the card is considered to be present. A debouncing feature of 4.5 ms typical is built-in. Pin PRES has an integrated current source to pin GND, pin PRES to VDD(INTREGD); the card is considered as present if at least one of the two inputs is true.
[3] [4] [5] [6] [7] [8] [9]
[10] Pin OFFN is an NMOS drain, using an internal pull-up resistor to VDD(INTREGD).
Table 9. Symbol ICC
Protection characteristics Parameter supply current Conditions shutdown current on pin VCC pin VCC pin CLK pin RST Min 95 135 -70 -20 -15 Typ 135 175 150 Max 185 225 +70 +20 +15 Unit mA mA mA mA mA C
IIO Tsd Table 10. Symbol tact tdeact td
input/output current shutdown temperature Timing characteristics Parameter activation time deactivation time delay time
pins I/O, AUX1 and AUX2
Conditions total sequence with the crystal oscillator external clock total sequence CLK sent to a card with the crystal oscillator td(start) = t3 td(end) = t5 CLK sent to card using an external clock td(start) = t3 td(end) = t5
[2] [2] [4] [1] [1] [1] [2] [3]
Min 35 35 35 35 160 35 160 3.2
Typ 80 4.5
Max 3000 240 100 3000 3090 150 240 12
Unit s s s s s s s ms
tdeb
[1] [2] [3] [4]
debounce time
See Figure 8 on page 15. See Figure 10 on page 16. See Figure 12 on page 18. See Figure 15 on page 21.
on pins PRES and PRESN
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IC card interface
tr 90 % 90 %
tf VOH (VOH + VOL)/2
10 %
t1
10 %
t2
VOL
001aai973
Fig 16. Definition of output and input transition times
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IC card interface
12. Application information
VDD(INTF)
MICROCONTROLLER VDD(INTF) VDD(INTF) ENCLKIN PORADJ AUX2UC AUX1UC TEST4 XTAL1 XTAL2 I/OUC
R1
R2
VDD(INTF) CMDVCCN TEST1
C5 100 nF
32 31 30 29 28 27 26 25 1 2 24 23 22
TEST3 OFFN RSTIN VDDI(REG) GND VDD(INTREGD) VCC RST
C1 470 nF
VDDI(REG)
C3 10 F C4 100 nF
TEST2 3 VDD(INTF) 4 CLKDIV2 5 CLKDIV1 6 VCC_SEL1 7 VCC_SEL2 8 I/O PRES PRESN
TDA8025
21 20 19 18 17
9 10 11 12 13 14 15 16 CONFIG VDD(INTREGD)
C2 220 nF
AUX2
AUX1
CGND C1 C2 C3 C4 K1
CARD CONNECTOR C5 C6 C7 C8 K2
CLK
RD
VDDI(REG)
001aai974
Refer to Table 8 on page 23 and Section 8.1 "Power supplies" on page 7 for detailed information on the VDD(INTF) restrictions.
Fig 17. Application diagram (3 V < VDDI(REG) < 3.6 V)
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VDD(INTF)
MICROCONTROLLER VDD(INTF) VDD(INTF) ENCLKIN PORADJ AUX2UC AUX1UC TEST4 XTAL1 XTAL2 I/OUC
R1
R2
VDD(INTF) CMDVCCN TEST1
C5 100 nF
32 31 30 29 28 27 26 25 1 2 24 23 22
TEST3 OFFN RSTIN VDDI(REG) GND VDD(INTREGD) VCC RST
C1 470 nF
VDDI(REG)
C3 10 F C3 10 F C4 100 nF
TEST2 3 VDD(INTF) 4 CLKDIV2 5 CLKDIV1 6 VCC_SEL1 7 VCC_SEL2 8 I/O PRES PRESN
TDA8025
21 20 19 18 17
9 10 11 12 13 14 15 16 CONFIG
C2 220 nF
AUX2
AUX1
CGND C1 C2 C3 C4 K1
CARD CONNECTOR C5 C6 C7 C8 K2
CLK
RD
VDDI(REG)
001aaj350
Refer to Table 8 on page 23 and Section 8.1 "Power supplies" on page 7 for detailed information on the VDD(INTF) restrictions.
Fig 18. Application diagram (3.6 V < VDDI(REG) < 5.5 V)
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13. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm
SOT617-1
D
B
A
terminal 1 index area E
A A1 c
detail X
e1 e 9 L 8 17 e
1/2 e
C b 16 vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area
24 32 Dh 0 2.5 scale E (1) 5.1 4.9 Eh 3.25 2.95 e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 25 X
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.25 2.95
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Fig 19. Package outline SOT617-1
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14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 20) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 12. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 20.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 13. Acronym ATR ESD ESR NMOS POR PMOS Abbreviations Description Answer To Request ElectroStatic Discharge Equivalent Series Resistance Negative-channel Metal-Oxide Semiconductor Power-On Reset Positive-channel Metal-Oxide Semiconductor
16. Revision history
Table 14. Revision history Release date 20090406 Data sheet status Product data sheet Change notice Supersedes Document ID TDA8025_1
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17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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19. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage supervisors . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDD(INTREGD) voltage supervisor with pin PORADJ connected to VDD(INTF) . . . . . . . . 9 8.2.4 VDD(INTF) voltage supervisor with external divider on pin PORADJ. . . . . . . . . . . . . . . . . . . 9 8.2.4.1 R1 and R2 resistor value calculation . . . . . . . . 9 8.3 Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.4 Input and output circuits . . . . . . . . . . . . . . . . . 13 8.5 Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6 Activation sequence . . . . . . . . . . . . . . . . . . . . 14 8.7 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.8 Deactivation sequence . . . . . . . . . . . . . . . . . . 18 8.9 VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 19 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 10 Thermal characteristics. . . . . . . . . . . . . . . . . . 22 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 Application information. . . . . . . . . . . . . . . . . . 31 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 14 Soldering of SMD packages . . . . . . . . . . . . . . 34 14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 34 14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 34 14.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 34 14.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 35 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 36 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 37 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18 Contact information. . . . . . . . . . . . . . . . . . . . . 37 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 April 2009 Document identifier: TDA8025_1

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